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automotive power data sheet rev. 1.0, 2013-06-19 TLF50211EL 2.2 mhz step-down regulator 500 ma, 5 v, low quiescent current
type package marking TLF50211EL pg-ssop-14 tlf50211 pg-ssop-14 data sheet 2 rev. 1.0, 2013-06-19 2.2 mhz step-down regulator 500 ma, 5 v low quiescent current TLF50211EL TLF50211EL 1overview ? 500 ma step down voltage regulator ? 5 v output voltage ? 2% output voltage tolerance ? low quiescent current (less than 45a at nominal battery voltage) ? integrated power transistor ? current mode pwm regulation ? pfm mode for light load current ? input voltage range from 4.75v to 45v ? 2.2 mhz switching frequency ? 100% duty cycle ? synchronization input ? very low shutdown current consumption (<2 a) ? soft-start function ? input undervoltage lockout ? suited for automotive applications: t j = -40 c to +150 c ? green product (rohs compliant) ? aec qualified description the TLF50211EL is a high frequency pwm step-down dc/ dc converter with an integr ated pmos power switch, packaged in a small pg-ssop-14 with exposed pad. the wide input voltage range from 4.75 to 45 v makes the TLF50211EL suitable for a wide variety of applications. t he device is designed to be used under harsh automotive environmental conditions. the switching frequency of nominal 2.2 mhz allows the use of small and cost -effective inductor s and capacitors, resulting in a low, predictable out put voltage ripple and in minimized consumption of board space. in light load condition the device operates in pulse frequency modulation (pfm) to optimize the efficiency. between the single pulses, all internal controlling circuitry is switched off to reduce the internal power consumption.
TLF50211EL overview data sheet 3 rev. 1.0, 2013-06-19 the TLF50211EL includes protection features such as a cycle-by-cycle current limitation, over-temperature shutdown and input under voltage lockout. the enable f unction, in shutdown mode with less than 2 a current consumption, enables easy power mana gement in battery-powered systems. the voltage regulation loop provides an excellent line and load regulation, t he stability of the loop is ensured by an internal compensation network. this compensation network combined with a current mode regulation control guarantees a highly effective line transient rejection. du ring start-up the integrated soft-start limits the inrush current peak and prevents from an output voltage overshoot.
data sheet 4 rev. 1.0, 2013-06-19 TLF50211EL block diagram 2 block diagram figure 1 block diagram 13 gnd enable oscillator 14 7 buck converter 11 fb swo 5 freq 1 n.c. en vs soft start ramp generator bandgap reference TLF50211EL over temperature shutdown 3 n.c. 8 n.c. int. supply 2 n.c. 6 n.c. 4 sync gnd 9 10 12 n.c.
TLF50211EL pin configuration data sheet 5 rev. 1.0, 2013-06-19 3 pin configuration 3.1 pin assignment figure 2 pin configuration 3.2 pin definitions and functions pin symbol function 1n.c. not connected. internally not connected. le ave open or connect to gnd. 2n.c. not connected. internally not connected. le ave open or connect to gnd. 3n.c. not connected. internally not connected. le ave open or connect to gnd. 4sync synchronization input connect to an external clock signal in order to synchronize/adjust the switching frequency. this feature is not functionally in pfm mode. 5freq frequency adjustment pin connect an external resistor to gnd to adjus t the switching frequency, do not leave open. in case the synchronization option is used, the resi stor must be dimensioned close to the desired synchronization frequency. 6n.c. not connected. internally not connected. le ave open or connect to gnd. 7fb feedback input connect this pin directly to the output capacitor. also input for internal power supply. the internal power supply is taken from the output voltage. 8n.c. not connected. internally not connected. le ave open or connect to gnd. 9gnd ground connect this pin directly with low inductive and broad trace to ground, do not leave open. 10 gnd ground connect this pin directly with low inductive and broad trace to ground, do not leave open. n.c. n.c. swo en 11 12 4 3 2 13 1 14 sync TLF50211EL n.c. gnd 5 freq 6 n.c. 7 fb gnd 10 9 n.c. 8 pg-ssop14 vs n.c.
data sheet 6 rev. 1.0, 2013-06-19 TLF50211EL pin configuration 11 swo buck switch output drain of the integrated power-pmos transistor. connect directly to the cathode of the catch diode and the buck circuit inductance. 12 n.c. not connected. internally not connected. le ave open or connect to gnd. 13 vs supply voltage input connect to supply voltage source. 14 en enable input switch to high level to enabl e the device, switch to low level to disable the device. exposed pad connect to heatsink area and gnd by low inductance wiring. pin symbol function
TLF50211EL general product characteristics data sheet 7 rev. 1.0, 2013-06-19 4 general product characteristics 4.1 absolute maximum ratings note: stresses above the ones listed here may cause perm anent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note: integrated protection functions are designed to prevent ic destruction under fault conditions described in the data sheet. fault conditions are considered as ?outside? normal operating range. protection functions are not designed for continuous repetitive operation. absolute maximum ratings 1) t j = -40 c to +150 c; all voltages with respect to ground (unless otherwise specified) 1) not subject to production test, specified by design pos. parameter symbol limit values unit conditions min. max. voltages 4.1.1 enable input v en -40 45 v ? 4.1.2 synchronization input v sync -0.3 5.5 v ? 4.1.3 6.2 v t < 10s 2) 2) esd susceptibility hbm according to ansi/esda/jedec js-001. 4.1.4 feedback input v fb -0.3 5.5 v ? 4.1.5 6.2 v t < 10s 2) 4.1.6 frequency adjustment pin v freq -0.3 5.5 v ? 4.1.7 6.2 v t < 10s 2) 4.1.8 buck switch output v swo -2.0 v vs + 0.3 v ? 4.1.9 supply voltage input v vs -0.3 45 v ? temperatures 4.1.10 junction temperature t j -40 150 c? 4.1.11 storage temperature t stg -55 150 c? esd susceptibility 4.1.12 esd resistivity v esd -2 2 kv hbm 4.1.13 esd resistivity to gnd v esd -500 500 v cdm 3) 3) esd susceptibility, charged device model ?cdm? eia/jesd22-c101 or esda stm5.3.1 4.1.14 esd resistivity corner pins to gnd v esd -750 750 v cdm 3)
data sheet 8 rev. 1.0, 2013-06-19 TLF50211EL general product characteristics 4.2 functional range note: within the functional range the ic operates as de scribed in the circuit description. the electrical characteristics are specifi ed within the conditions given in the re lated electrical ch aracteristics table. 4.3 thermal resistance pos. parameter symbol limit values unit conditions min. max. 4.2.1 supply voltage v s 4.75 45 v ? 4.2.2 buck inductor l bu 3.3 22 h ? 4.2.3 buck capacitor c bu1 10 50 f ? 4.2.4 buck capacitor esr esr bu1 0.015 0.100 ? 1) 1) see section ? ?application information? on page 22 ? for loop compensation requirements and refer to application note for dimensioning the output filter. 4.2.5 junction temperature t j -40 150 c? pos. parameter symbol limit values unit conditions min. typ. max. 4.3.1 junction to case 1) 1) not subject to production test, specified by design. r thjc ?10?k/w? 4.3.2 junction to ambient 1) 2) 2) specified r thja value is according to jedec 2s2p (jesd 51-7) + (jesd 51-5) and jedec 1s0p (jesd 51-3) + heatsink area at natural convection on fr4 board. r thja ?47?k/w2s2p 4.3.3 r thja ? 54 ? k/w 1s0p + 600 mm 2 4.3.4 r thja ? 64 ? k/w 1s0p + 300 mm 2
TLF50211EL buck regulator data sheet 9 rev. 1.0, 2013-06-19 5 buck regulator 5.1 description the TLF50211EL is a monolithic current mode step down converter with adjustable switching frequency f osc . it is capable to operate either in pulse width modulation (pwm) or in pulse frequency modulation (pfm) mode. 5.1.1 regulator loop power stage: the supply voltage is connected to pin vs. between pin vs and pin swo there is an internal shunt resistor and the internal pmos power stage. the pmos is driven by the driver stage. regulator block: the feedback signal v fb is connected to pin fb. between pin fb and pi n gnd is an internal resistor divider. an error amplifier and a comparator are connected to this resistor divider: the error amplifier ea-gmv, which is controlling the output voltage in pw m mode, and the pfm comparator, whic h will switch the TLF50211EL into pfm mode and trigger the pulses. the error amplifier ea-gmv is connected to the pwm comparator. the regulation loop operates in current mode: the ou tput current of ea-gmv is subtracted fr om the sum of the current loop cs- gmi and the slope compensation i slope . the result is evaluated by pwm comp (a current comparator). the output of pwm comp defines duty cycle (pulse-width-modulated signal) in pwm mode. the slope compensation added to the signal from the error amplifier ea-gmv to the pwm comparator ensures that no sub harmonics will occur on the input current. the pwm comparator output and the pfm comparator output are connected to the pwm /pfm logic. an external resistor at pin freq is required to set the switching frequency (for details please refer to chapter 7 module oscillator). the tlf502 11el may also be synchronized to an exter nal frequency. in this case an external clock signal should be connected to pi n sync. the frequency settin g resistor at pin freq is still necessary, it has to be selected acco rding to the desired synchronizati on frequency (for details please refer to chapte r 7 oscillator). the TLF50211EL can only be synchronized to an external frequency source in pwm mode, this function does not work in pfm mode. the clock manager is clocking the pwm/pfm logic. the pwm/pfm logic is triggering the driver to apply pulses to the internal pmos power stage. safety features: the shunt resistor in line wit h the internal pmos power stage (between pin vs and the power stage) is connected to a current sense amplifier cs-gml. it detects the voltage above the shunt resistor. the amplifier creates a signal which shuts the pulse down in case that the shunt voltag e exceeds the reference limit. the current limitation acts as a cycle-by-cycle limitation. cycle-by -cycle limitation means, t hat every pulse is switched off as soon as the current through the pmos exceeds the buck peak over current limit i buoc . the next pulse star ts and will also be switched off as soon as the current limit is exceeded a gain. this results in a lowe red output voltage whilst the output current is limited to a certain value. input undervoltage shutdown: if t he input voltage is below the input undervoltage shutdown threshold v s,off the device will shut down.
data sheet 10 rev. 1.0, 2013-06-19 TLF50211EL buck regulator output overvoltage protection: if th e output voltage ex ceeds the pfm threshold the device will switch from pwm to pfm. pulses will then be gen erated only depe nding on the value of the output voltage v cc . soft start function: an integrated soft start function of duration t start ensures, that the inrush current will be limited. after an over-temperature shutdown the regulator always restarts with a soft start. over-temperatur e shutdown: an internal temper ature sensor detects the temper ature of the device. it will be switched off if the junction temperature exceeds the over temperature shutdown threshold t j,sd and restart with a certain hysteresis t j,sd_hyst (for details please refer to chapter 6, enable and thermal shutdown ). biasing: the internal biasing is taken from pin vs as well as from pin fb (connected to v cc ) (for details please refer to chapter 6, enable and thermal shutdown ). thus the power consumption from the supply voltage v s can be minimized. figure 3 block diagram buck regulator + - driver + - cs-gmi ea-gmv pwm pfm logic clock manager pwm comp softstart gated vs swo fb freq sync_in gnd pfm comparator + - slope comp. vbg clk ck_a
TLF50211EL buck regulator data sheet 11 rev. 1.0, 2013-06-19 5.1.2 pwm (pulse widt h modulation) mode under normal condit ions the TLF50211EL will operate wit h a constant swit ching frequency f osc in pwm mode. the ratio between switch-on-time t on and switch-off-time t off is mainly determined by the ratio between the input voltage v s and the output voltage v cc and is influenced by the output current i cc . in pwm mode the device may operate with 100% duty cycl e, in this case the inte rnal pmos is constantly conducting current. the current limitation feature is operating under this condition. if the switch-on-time t on should theoretically be below the minimum threshold t on,min (due to low load or due to the ratio between input voltage v s and output voltage v cc depending on the switching frequency), it will be reduced to the minimum value switch-on-time t on,min and stay there. as a cons equence the output voltage v cc will increase. the pfm comparator detects the pfm threshold and will then switch the device into pfm mode. there is no possibility to di sable the pfm function. 5.1.3 pfm (pulse fre quency modulation) mode to optimize the efficiency and to reduce the current co nsumption, the TLF50211EL auto matically switches to pfm mode under low load conditions. in pf m mode the internal power stage including the driver stage is switched off and will only be switched on for applyi ng pulses to charge the output capacitor. the pulses will be created by monitoring the voltage of th e output filter capacitor c out . thus in pfm mode the repetition time of pulses depend on the output current and/or the ratio between input voltage v s and output voltage v cc . transition from pwm to pfm: figure 4 is showing the transition from pulse width m odulation to pulse frequency modulation under the assumption, that the input voltage v s will be constant and on ly the output current i cc will vary. the diagram shows the principle, in reality the signals mi ght look slightly different. the diagram is without scale in respect of time, voltage and current values. starting from left of the figure a certain output current, here named i 1 , is applied to the regula tor output. th is results in a duty cycle d 1 with the on-time t on1 of the internal power stage. the switching frequency f osc is constant as set by the frequency setting resistor r freq . the regulator is in pwm mode, the output voltage is v ref_pwm which is equal to v fb in pwm mode. at point t 1 the output current decreases from i 1 to a lower i 2 . this results in a duty cycle d 2 with the on-time t on2 of the internal power stage. due to the reduced output load the on-time t on2 is shorter (the regulator is in discontinuous conduction mode dcm) than t on1 . the switching frequency f osc is constant as set by the frequency setting resistor r freq . the regulator is still in pwm mode, the output voltage is v ref_pwm which is equal to v fb in pwm mode. in continuous conduction mode ccm the variation from t on1 to t on2 will be very small due to smaller conduction losses. at point t 2 the output current decreases again from i 2 to a lower i 3 . as a consequence the on-time t on will be reduced also. the output current i 3 is so low, that the on-time t on3 would be smaller than the t on,min . the regulator does not allow a on-time smaller than t on,min . therefore we can say that the output current i 3 is under the imaginary current threshold for transition from pwm to pfm i pwm/pfm . with the pulse staying at on-time t on,min the output voltage v cc will rise. the regulator is still in pw m mode, but the out put voltage rises.
data sheet 12 rev. 1.0, 2013-06-19 TLF50211EL buck regulator at point t 3 after a normal time period t pwm as adjusted by the frequency setting resistor r freq , a further pulse of the duration t on,min is applied, the output voltage v cc keeps on rising. the regu lator is still in pwm mode. at point t 4 the output voltage v cc touches (or exceeds) the voltage thre shold for transition from pwm to pfm v pwm/pfm . the regulator is now switching in ternally from pwm to pfm. in pf m mode the power consumption of the internal blocks is reduced. the reference for the output voltage v cc is switched from v ref_pwm (which is equal to v fb in pwm mode) to v ref_pfm (which is equal to v fb in pfm mode). the reference for v fb in pfm mode is higher than the reference in pwm mode to avoid voltage dumps at the output voltage v cc due to sudden load steps and to give the regulator more re action time to switch back to pwm mode. the regulator is now in pfm mode, the output voltage is v ref_pfm which is equal to v fb (or slightly higher) in pfm mode. the output voltage v cc is monitored and as soon as it touches the pfm reference voltage v ref_pfm a pulse of the on-time t on,min is triggered. the time between two pulses is depending on the di scharging of the output capacitor c out . figure 4 pwm to pfm transition (timing diagram) time output current time switching signal time output voltage i 1 i 2 i 3 i pwm/pfm d 1 d 2 t pwm t pwm d 3 t 1 t 2 t 3 t 4 v ref_pwm v ref_pfm v pwm/pfm switch to pfm mode t on1 t on2 t on,min t pwm
TLF50211EL buck regulator data sheet 13 rev. 1.0, 2013-06-19 transition from pfm to pwm: figure 5 is showing the transition from pulse frequency modulation to pulse width modulation under the assumption, that the input voltage v s will be constant, and only the output current i cc will vary. the diagram shows the principle, in reality the signals mi ght look slightly different. the diagram is without scale in respect of time, voltage and current values. starting from left of the figure a certain output current, here named i 3 , is applied to the regulator output. i 3 shall be below the imaginary current threshold for transition from pfm to pwm i pfm/pwm . the regulator is in pfm mode, the output voltage is v ref_pfm , which is equal to v fb in pfm mode (or slightly higher). pulses of the duration t on,min are triggered whenever the output voltage v cc touches the pfm reference voltage v ref_pfm . at point t 5 the output current increases from i 3 to a higher i 2 , that shall be above the imaginary current threshold for transition from pfm to pwm i pfm/pwm . due to the higher output curren t more pulses of the duration t on,min have to be triggered, the frequency of thes e pulses is monitored. the frequency of these pulses increases until it is higher than the switching frequency f osc set by the frequency setting resistor r freq . the regulator is still in pfm mode at point t 6 the frequency monitoring detects that the frequen cy of the pfm pulses is being higher than the frequency threshold for transition from pfm to pwm f pfm/pwm . therefore the regulator switches back to pwm mode. this results in a certain duty cycle d 2 with the on-time t on2 of the internal power stage. the time period t pwm is as adjusted by the frequency setting resistor r freq . figure 5 pfm to pwm transition (timing diagram) time output current time switching signal time output voltage i 2 i 3 i pfm/pwm d 2 t pwm t 5 v ref_pwm v ref_pfm v pwm/pfm switch to pwm mode t on2 t on,min t 6 t on,min
data sheet 14 rev. 1.0, 2013-06-19 TLF50211EL buck regulator frequency variation during pwm/pfm transition: figure 6 is showing the transition from pulse frequency modul ation to pulse width modulation (and vice versa) in relation to output current and switching frequency. the diagram shows the principle, in reality the signals might be slightly different. the diagram is without sca le in respect of frequency and current values. the transition from pwm to pfm is shown in a grey line. starting from right the switching frequency f pwm is constant as set by the frequency setting resistor r freq . the output current i cc is decreasing. as soon as the output current i cc is below the imaginary current threshold for transition from pwm to pfm i pwm/pfm , the regulator will be switched from pwm to pfm mode depend ing on the output voltage v cc . with the output current i cc decreasing, the switching frequency will also decrease, as the pulse s are triggered by monitoring the output voltage v cc at capacitor c out . the transition from pfm to pwm is shown in a black line. starting from left the switching frequency is increasing with the increasing output current i cc . as soon as the switching frequency is crossing t he frequency threshold for transition from pfm to pwm f pfm/pwm (which is above the switching frequency f osc set by the frequency setting resistor r freq ) the regulator will switch from pfm to pwm. t figure 6 pwm <-> pfm transitions output current (log.scale) switching frequency (log.scale) pfm to pwm pwm to pfm f pfm/pwm f pwm i pwm/pfm i pfm/pwm
TLF50211EL buck regulator data sheet 15 rev. 1.0, 2013-06-19 5.2 electrical characteristics electrical characteristics: buck regulator v s = 6.0 v to 40 v, t j = -40 c to +150 c, all voltages with respect to ground (unless otherwise specified) pos. parameter symbol limit values unit conditions min. typ. max. 5.2.1 output voltage v fb 4.90 5.00 5.10 v v en = 5.0v 7 v < v s < 12v 100 ma < i cc < 610 ma pwm mode 5.2.2 output voltage v fb 4.90 5.10 5.30 v v en = 5.0v 10v < v s < 35v i cc = 100 a pfm mode 5.2.3 power sta ge on-resistance r on ?1.52.3 tested at 100 ma, v s = 7.0v 5.2.4 buck peak over current limit i buoc 0.85 ? 1.7 a ? 5.2.5 current transition rise/fall time t r ? 100 ? ma/ns 1) 1) specified by design. not subject to production test. 5.2.6 maximum duty cycle d max ?? 100% 2) 2) consider ? chapter 4.2, functional range ?. 5.2.7 minimum switch on-time t on,min ?100? ns 1) 5.2.8 minimum switch off- time t off,min ?200? ns 1) pfm mode 5.2.9 soft start ramp t start 300 450 750 s v fb rising from 5% to 95% of v fb,nom 5.2.10 input under voltage shutdown threshold v s,off 3.75 ? ? v v s decreasing 5.2.11 input voltage startup threshold v s,on ? ? 4.75 v v s increasing 5.2.12 input under voltage shutdown hysteresis v s,hyst 130 300 ? mv ? 5.2.13 voltage thres hold for transition from pwm to pfm v pwm/pfm ?? 5.3v 1) 5.2.14 frequency ratio for transition from pfm to pwm f pfm/pwm / f osc ?1.20? ? 1)
data sheet 16 rev. 1.0, 2013-06-19 TLF50211EL buck regulator 5.3 performance graphs typical performanc e characteristics load regulation pwm mode v s = 12 v; t j = - 43 c load regulation pwm mode v s = 12 v; t j = + 25 c load regulation pwm mode v s = 12 v; t j = + 150 c 5,000 5,025 5,050 5,075 5,100 vfb (v) 4,900 4,925 4,950 4,975 50 150 250 350 450 550 650 icc (ma) 5,000 5,025 5,050 5,075 5,100 vfb (v) 4,900 4,925 4,950 4,975 50 150 250 350 450 550 650 icc (ma) 5,000 5,025 5,050 5,075 5,100 vfb (v) 4,900 4,925 4,950 4,975 50 150 250 350 450 550 650 icc (ma)
TLF50211EL buck regulator data sheet 17 rev. 1.0, 2013-06-19 typical performanc e characteristics line regulation pfm mode i cc = 100 a; t j = - 43 c line regulation pfm mode i cc = 100 a; t j = + 25 c line regulation pfm mode i cc = 100 a; t j = + 150 c power stage on resistance: black t j = + 25 c light grey t j = - 43 c, dark grey t j = + 150 c 5 5,016 5,032 5,048 5,064 5,08 5,096 5,112 5,128 5 10 15 20 25 30 35 40 45 vfb (v) vs (v) 5 5,016 5,032 5,048 5,064 5,08 5,096 5,112 5,128 5 10 15 20 25 30 35 40 45 vfb (v) vs (v) 5 5,016 5,032 5,048 5,064 5,08 5,096 5,112 5,128 5 10 15 20 25 30 35 40 45 vfb (v) vs (v) 0,600 0,800 1,000 1,200 1,400 - vswo (v) 0,000 0,200 0,400 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 vs - iswo(a)
data sheet 18 rev. 1.0, 2013-06-19 TLF50211EL buck regulator efficiency for v s = 13 v, f osc = 1.65 mhz, l out = 4.7 h efficiency for v s = 13 v, f osc = 1.65 mhz, l out = 10 h efficiency for v s = 13 v, f osc = 2.2 mhz, l out = 4.7 h efficiency for v s = 13 v, f osc = 2.2 mhz, l out = 10 h 10,00% 20,00% 30,00% 40,00% 50,00% 60,00% 70,00% 80,00% 90,00% 0 100 200 300 400 500 600 i cc (ma) 0,00% 10,00% 20,00% 30,00% 40,00% 50,00% 60,00% 70,00% 80,00% 90,00% 0 100 200 300 400 500 600 i cc (ma) 10,00% 20,00% 30,00% 40,00% 50,00% 60,00% 70,00% 80,00% 90,00% 0 100 200 300 400 500 600 i cc (ma) 0,00% 10,00% 20,00% 30,00% 40,00% 50,00% 60,00% 70,00% 80,00% 90,00% 0 100 200 300 400 500 600 i cc (ma)
TLF50211EL enable and thermal shutdown data sheet 19 rev. 1.0, 2013-06-19 6 enable and thermal shutdown 6.1 description a valid high level at pin en ( v en,hi ) turns the regulator on, a valid low level at pin en ( v en,lo ) turns the regulator off. in off state the current consumption of the device is less than 2a. an integrated pull down resistor at pin en ( r en,int ) ensures, that the device is switched off, if pin en is left open. the integrated thermal shutdown function turns off the power switch in case of overtemperature. the typ. junction shutdown temperature is 175c, with a min. of 155c. after cooling down, the ic will au tomatically restart with a soft start into normal operation. the thermal shutdown is an integrated protection function designed to prevent ic destruction when operating under fault conditi ons. it should not be used for normal operation. 6.2 electrical character istics module enable, bias and thermal shutdown electrical characteristics: enable, bias and thermal shutdown v s = 6.0 v to 40 v, t j = -40 c to +150 c, all voltages with respect to ground (unless otherwise specified) pos. parameter symbol limit values unit conditions min. typ. max. enable en 6.2.1 current consumption, shut down mode i q,off ?0.12a v en = 0v; t j < 105c; v s = 16v 6.2.2 current consumption of v cc i q,on,v_cc ??60a v en = 5.0v; v s = 16v; v cc = 5.4v; t j < 105c; pfm mode 6.2.3 current consumption of v s i q,on,v_s ? 1520a v en = 5.0v; v s = 16v; v cc = 5.4v; t j < 105c; pfm mode 6.2.4 enable high signal valid v en,hi 3.0 ? ? v ? 6.2.5 enable low signal valid v en,lo ??0.8v? 6.2.6 enable hysteresis v en,hy 50 200 400 mv ? 6.2.7 enable high input current i en,hi ??3a v en = 16v 6.2.8 enable low input current i en,lo ?0.11a v en = 0.5v 6.2.9 enable, internal resistor to gnd r en,int 71220 ? v en = 3v internal over temperature protection 6.2.10 over temperature shutdown t j,sd 155 175 195 c 1) 1) specified by design. not subject to production test. 6.2.11 over temperature shutdown hysteresis t j,sd_hyst -15?k 1)
data sheet 20 rev. 1.0, 2013-06-19 TLF50211EL oscillator 7 oscillator 7.1 description the oscillator supplies the device with a constant frequency. the power swit ch will be switched on and off with a constant frequency f osc . the time period t pwm is derived from this frequency and some safety functions are synchronized to this frequency. the oscillator frequency can be set by connecting an external resistor r freq between pin freq and gnd using the following table (selected values, for more precise setting please refer to figure 7 below). figure 7 switching frequency f osc versus frequency setting resistor r freq . the turn-on frequency can optionally be set externally via the sync pin. in this case the synchronization of the pwm-on signal refers to the falling edg e of the sync-pin input signal. in case the synchronization to an external clock signal is not needed, the sync pin should be co nnected to ground. the frequency setting resistor r freq is also necessary for sync option and must be dimensioned according to the desired synchronization frequency (the ratio between synchronization and internal fr equency has to be less than or equal to 1). the synchronization function is not available in pfm mode. frequency setting resistor 7.1.1 oscillator frequency f osc 2400 2250 1800 1330 1100 khz 7.1.2 frequency adjusting resistor r freq 39 43 56 82 100 k 1 1,15 1,3 1,45 1,6 1,75 1,9 2,05 2,2 2,35 2,5 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 switching frequency [mhz] resistor at freq pin [k ]
TLF50211EL oscillator data sheet 21 rev. 1.0, 2013-06-19 7.2 electrical character istics module oscillator electrical characteristics: module oscillator v s = 6.0 v to 40 v, t j = -40 c to +150 c, all voltages with respect to ground (unless otherwise specified) pos. parameter symbol limi t values unit conditions min. typ. max. frequency setting freq 7.2.1 oscillator frequency spread f osc 2025 2250 2475 khz v sync = 0v; r freq = 43k synchronization sync 7.2.2 synchronization capture range f sync 1500 ? 2200 khz ? 7.2.3 sync signal high level valid v sync,h 2.9 ? ? v 1) 1) synchronization of pwm-on signal to falling edge. 7.2.4 sync signal low level valid v sync,l ??0.8v 1) 7.2.5 sync input internal pull-down r sync,int 0.15 0.25 0.40 m v sync = 5v 7.2.6 sync signal minimum high time t sync,h, min 25 ? ? ns ? 7.2.7 sync signal minimum low time t sync,l,min 25 ? ? ns ?
data sheet 22 rev. 1.0, 2013-06-19 TLF50211EL application information 8 application information note: the following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. figure 8 application diagram note: this is a very simplified example of an application circuit. the function must be verified in the real application figure 9 bill of material for application diagram c in3 d in l in enable oscillator buck converter fb swo freq en vs soft start ramp generator bandgap reference TLF50211EL over temperature shutdown n.c. n.c. d catch c out v s v cc l out int. supply n.c. sync r5 c in2 c in1 l in , c in1 and c in3 recommended for suppression of eme, d in depending on application gnd gnd n.c. n.c. n.c. c in2 c in3 c out l out d catch - - - - r5 100nf/50v 47f/50v 10f/25v part-no. value 1a/100v type manufacturer 10h mss1278 t avx ceramic ceramic remark coilcraft 10bq100 schottky international rectifier 43 k ? - - - -- - - - 0.25 w electrolytic 4.7 h also possible f os c set to 2.2 mhz for improving eme 1 a current capability - - - - panasonic avx avx
TLF50211EL application information data sheet 23 rev. 1.0, 2013-06-19 8.1 general layout recommendations introduction: a switch mode step down converter is a potential source of electromagnetic disturbances which may affect the environment as well as the device itself and cause spor adic malfunction up to damages depending on the amount of noise. in principal we may consider the following basic effects: ? radiated magnetic fields caused by circular currents, occurring mostly with the switching frequency and their harmonics; ? radiated electric fields, often caused by (voltage) oscillations; ? conducted disturba nces (voltage spikes or oscillations) on the lines, mostly in put and output lines. radiated magnetic fields: radiated magnetic fields are caused by circular currents occurring in so called ?current windows?. these circular currents are alternating currents which are driven by th e switching transistor. the alternating current in these windows are driving magnetic fields. th e amount of magnetic emissions is mainly depending on the amplitude of the alternating current and the size of the so-called ?wi ndow? (this is the area, whic h is defined by the circular current paths. we can divide into two windows: ? the input current ?window? (path consisting of c in2, c in3 , l out and c out ): only the alternate content of the input current i s is considered; ? the output current ?window? (path consisting of d catch , l out and c out ): output current ripple i. the area of these ?windows? has to be kept as small as possible, with the relating elements placed next to each others as close as possible. it is highly recommended to use a ground plane as a single layer which covers the complete regulator area with all components shown in the application diagram. all connections to ground shall be as short as possible. radiated electric fields: radiated electric fields are caused by voltage oscillations occurring by st ray inductances and stray capacitances at the connection between internal power stage (pin swo), freewheeling diode d catch , and output capacitor c out . they are also of course influenced by the commutation of the current from the internal power stage to the freewheeling diode d catch . their frequencies might be above 100 mhz. therefore, it is recommended to use a fast schottky diode and to keep the connections in this ar ea as low inductive as possible. this can be achieved by using short and broad connections and by arranging the related parts as close as possible. following the recommendation of using a ground layer these lo w inductive connections will form together with th e ground layer small capacitances which are desirable to damp the slope of these oscillati ons. the oscillation s use connections or wires as antennas, this effect can also be minimized by the short and broad connections.
data sheet 24 rev. 1.0, 2013-06-19 TLF50211EL application information conducted disturbances: conducted disturbances are vo ltage spikes or voltage osc illations, occurring permanently or by occasion mostly on the input or output connections. comparable to the radi ated electric fields they are caused by voltage stage, freewheeling diode d catch , and output capacitor c out . their frequencies might be above 100 mhz. they are supe r positioned to the input and output voltage and might therefore disturb other comp onents of the application. the countermeasures against conduc ted disturbances are similar to the radiated electric fields: ? it is recommended to use short and thick connecti ons between the single parts of the converter; ? all parts shall be mounted close together; ? additional filter capacitors (ceramic, with low esr i.e c in3 in the application diagram) in parallel to the output and input capacitor and as close as possible to the swit ching parts. input and load current must be forced to pass these devices, do not connect them via thin lines. recommended values from 10nf to 220nf; ? for the input filter a so called ? filter for maximum suppression might be necessary, which requires additional capacitors on the input. 8.1.1 additional information please contact us: ? for information regarding the pin fmea; ? for existing application notes wit h more detailed information about the possibilities of this device; ? for further information you may contact http://www.infineon.com/
TLF50211EL package outlines data sheet 25 rev. 1.0, 2013-06-19 9 package outlines figure 10 package outline pg-ssop-14 green product (rohs compliant) to meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. gree n products are rohs-compliant (i.e pb-free finish on leads and suitable for pb-free soldering according to ipc/jedec j-std-020). pg-ssop-14-1,-2,-3-po v02 1 7 14 8 14 17 8 14x 0.25 ?.05 2) m 0.15 d c a-b 0.65 c stand off 0 ... 0.1 (1.45) 1.7 max. 0.08 c a b 4.9 ?.1 1) a-b c 0.1 2x 1) does not include plastic or metal protrusion of 0.15 max. per side 2) does not include dambar protrusion bottom view ?.2 3 ?.2 2.65 0.2 ?.2 d 6 m d 8x 0.64 ?.25 3.9 ?.1 1) 0.35 x 45? 0.1 cd +0.06 0.19 8 ? max. index marking exposed diepad for further package information, please visit our website: http://www.infineon.com/packages . dimensions in mm
data sheet 26 rev. 1.0, 2013-06-19 TLF50211EL revision history 10 revision history rev version date changes rev 1.0 2011-11-03 initial data sheet
edition 2013-06-19 published by infineon technologies ag 81726 munich, germany ? 2013 infineon technologies ag all rights reserved. legal disclaimer the information given in this docu ment shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infineo n technologies hereby disclaims any and all warranties and liabilities of any kind, including wit hout limitation, warranties of non-infringement of in tellectual property rights of any third party. information for further information on technology , delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contai n dangerous substances. for information on the types in question, please contact the neares t infineon technologies office. infineon technologies components may be used in life-s upport devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safe ty or effectiveness of that de vice or system. life support devices or systems are intended to be implanted in the hu man body or to support an d/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

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